Due to the increased portion of Static Random Access Memory (SRAM) arrays in the total chip area of modern chips, device dimensions in SRAM must be continuously scaled. With shorter device channels and narrower widths, intrinsic device fluctuations and random mismatches among adjacent devices are significantly increased due to, e.g., random dopant fluctuations, short-channel effects, and narrow-width effects; thus, the stability of SRAM degrades with technology scaling.
The well-known conventional six transistor SRAM is described, e.g., in Hodges & Jackson's textbook “Analysis and Design of Integrated Circuits,” 2d edition, at pages 364-68 (New York, McGraw Hill, 1988). The conventional SRAM has its worst stability during the READ mode because the voltage at the storage node having a “zero” logic value rises during the READ cycle. If this increased node voltage is larger than the trip voltage of the inverter, the stored logic values will be flipped and data will be lost.
U.S. Pat. No. 6,198,656 to Zhang discloses an asymmetric memory cell for single-ended sensing. An apparatus including an asymmetrical memory cell having a first inverter and a second inverter is provided. The first inverter is larger than the second inverter.
U.S. Pat. No. 5,673,230 to Kuriyama discloses a semiconductor memory device capable of operating at high speed and stably even under low power supply voltage. A memory cell includes a read/write word line R/WL1 driving an access transistor Q1 in read and write operations and a write word line WL1 driving an access transistor Q2 in the write operation. In the write operation, both access transistors Q1 and Q2 are driven, and storage information is written in the memory cell by a bit line and a complementary bit line having potentials complementary to each other. On the other hand, in the read operation, only access transistor Q1 is rendered conductive, and storage information is read out through the bit line. Since access transistor Q2 is rendered nonconductive, a P type TFT transistor and an N type transistor operate as a complementary metal oxide semiconductor (CMOS) type inverter having a large voltage gain. Therefore, a sufficient operating margin is secured even in the read operation.
K. Takeda et al. have proposed “A Read-Static-Noise-Margin-Free SRAM Cell for LOW-Vdd and High-Speed Applications in 65 nm CMOS Technology with Integrated Column-Based Dynamic Power Supply” as set forth in Dig. Tech. Papers, ISSCC, pp. 478-479, February 2005. The proposed cell employs seven transistors. The additional transistor and a required extra word line increase the total cell area and the proposed cell also presents additional design considerations.
Thus, conventional symmetrical 6-T cells may be unstable when scaled to small sizes, and while the so-called asymmetrical SRAM cell can achieve an improved static noise margin (SNM) as compared to a conventional symmetrical SRAM cell, there are practical limits, due to device size considerations, to obtain further improvement in the SNM. The 7-T approach has limitations as set forth in the preceding paragraph.
It would be desirable to overcome the limitations in previous approaches.